This invention relates to an apparatus and method for suspending I/O control processing in response to system errors. More specifically, the present invention relates to a processing system in which an I/O control processing unit having an instruction processing unit for processing system I/O instructions and a bus arbiter for controlling priority in information transfer on a shared bus, in which an apparatus is provided for, in response to a system error indication, suspending instruction processing unit operation in a known state and bus arbiter operation
Digital computer systems implement modules which perform specific functional operations. These functional modules utilize clock signals for operation timing. Specifically, the system includes error indicators for detecting module operation errors. Once an error is detected it is desirable to evaluate and correct the error. In many cases the system clocks must be stopped instantly to capture the state of the machine for error checking. However, instantaneous halting of the clocks may cause data integrity problems and, in most instances, the machine would have to be put through an initial machine load (IML) state. The placing of the system in the IML state is a process of setting all latches in the processor to a known state. However, typically placing the system in the IML state is a time-consuming process that is a major interruption of normal system program execution.
With particular reference to I/O interfaces for retry and recovery following a machine check or error condition, typically the system clocks are also instantaneously stopped. In addition, arbitration of new bus requests by I/O devices on an address/data/communications (ADC) bus, typically shared by all I/O devices, to the I/O interface are inhibited. However, as previously mentioned, instantaneous stopping of the clocks may cause data integrity problems due to the incomplete state of operations between modules.
In software debugging application, it is desirable to halt system activity in order to interrogate the system. Again, instantaneous stopping of the system clocks to capture the state of the system may result in data integrity problems. In all conditions of retry, recovery and debug following stoppage of the system, there is a high probability that the system state is unknown which may seriously affect system operation if the clocks are immediately restarted. In order to insure proper operation of the system upon restart, all latches must be reset to a known state, such as through the initial machine load process.
An improved system may avoid the requirement of placing the system, upon detection of an error condition, in the IML state by placing the system into a known state prior to the stopping of the system clocks. Placing of the system into a known state prior to clock stopping would greatly facilitate restarting of the clocks and the processor upon correction of error condition.